Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations

D
DFT
2006
21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)
Abstract - Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations

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	Similar Articles Articles by Fengming Zhang Articles by Warren Necoechea Articles by Peter Reiter Articles by Yong-Bin Kim Articles by Fabrizio Lombardi

21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)

Arlington, Virginia, USA

October 04-October 06

ISBN: 0-7695-2706-X

	ASCII Text	x
	Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi, "Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 486-494, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.

	BibTex	x
	@article{ 10.1109/DFT.2006.38, author = {Fengming Zhang and Warren Necoechea and Peter Reiter and Yong-Bin Kim and Fabrizio Lombardi}, title = {Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {1550-5774}, pages = {486-494}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.38}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations SN - 1550-5774 SP486 EP494 A1 - Fengming Zhang, A1 - Warren Necoechea, A1 - Peter Reiter, A1 - Yong-Bin Kim, A1 - Fabrizio Lombardi, PY - 2006 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Fengming Zhang, LTX Corporation, USA

Warren Necoechea, LTX Corporation, USA

Peter Reiter, LTX Corporation, USA

Yong-Bin Kim, Northeastern University, USA

Fabrizio Lombardi, Northeastern University, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.38

This paper presents two load board designs for hierarchical calibration of largely populated ATE. Compound dot technique and phase detector are used on both boards to provide automatic and low cost calibration of ATE with or without a single reference clock. Two different relay tree structures are implemented on the two boards with advanced board design techniques for group offset calibration. Various error sources have been identified and analyzed on both boards based on SPICE simulations and real measurements. TDR measurement compares the two approaches and shows that the two load boards give a maximum of 37ps group timing skew and can be calibrated out by the calibration software.

Citation:

Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi, "Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations," dft, pp.486-494, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006

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