The paper addresses here the fault model of particular type of manufacturing defects in the metal layers of deep sub-micron (DSM) chips, e.g. conductive particle contamination, bad handling or under-etching defects in the pair of parallel interconnects which lead to both severe non-zero resistive bridging fault and increased crosstalk coupling fault between the on-chip aggressor-victim interconnects. The developed fault model is very helpful in analyzing the severity of defect and can also be utilized for determination of it?s critical value, below which device will continue to behave as defect tolerant, however, exceeding the critical value the defect may manifest other complex functionality and reliability problems of the device. Experimental simulations carried out with Philips CMOS12 (130 nm) technology parameters reveal twofold electrical effect of the defect. For instance, non-zero resistive bridging fault has major effect on the final steady-state value of the victim?s output signal waveform, whereas the crosstalk coupling fault has major effect on the delay as well as crosstalk glitch height of the victim?s output waveform. It has been further observed that the defect?s severity is highly dependent on defect?s location because the same defect is less severe (measured in terms of victim?s delay and crosstalk glitch height) when the defect is located at the near end side of interconnects, whereas it becomes more and more severe when the same defect is located in the middle and far end side of interconnects.