21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06) Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method Arlington, Virginia, USA October 04-October 06 ISBN: 0-7695-2706-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.27
In this paper, we apply a technique to improve diagnosis resolution for delay faults. The method analyze the structure of test paths to find the bottleneck of the diagnosis process. Then we use the information to search for additional paths (by extending from the current paths) in order to effectively cut down the number of faulty candidates. The experimental result shows that the proposed technique can reduce the efforts of diagnosis by a meaningful amount. In ISCAS?89 benchmarks, the method can improve the average ranks of injected defects in the suspect list from 9.14 to 5.97 as injected delay size is 1% of longest paths.
Citation:
Ying-Yen Chen, Jing-Jia Liou, "Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method," dft, pp.428-438, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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