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21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)

Bilateral Testing of Nano-scale Fault-tolerant Circuits (PDF)

Arlington, Virginia, USA

October 04-October 06

ISBN: 0-7695-2706-X

	ASCII Text	x
	Lei Fang, Michael S. Hsiao, "Bilateral Testing of Nano-scale Fault-tolerant Circuits," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 309-317, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.

	BibTex	x
	@article{ 10.1109/DFT.2006.17, author = {Lei Fang and Michael S. Hsiao}, title = {Bilateral Testing of Nano-scale Fault-tolerant Circuits}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {1550-5774}, pages = {309-317}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.17}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Bilateral Testing of Nano-scale Fault-tolerant Circuits SN - 1550-5774 SP309 EP317 A1 - Lei Fang, A1 - Michael S. Hsiao, PY - 2006 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Lei Fang, Virginia Tech, USA

Michael S. Hsiao, Virginia Tech, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.17

As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge.

In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS?85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.

Citation:

Lei Fang, Michael S. Hsiao, "Bilateral Testing of Nano-scale Fault-tolerant Circuits," dft, pp.309-317, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006

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