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21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)
An Approach to Minimizing Functional Constraints
Arlington, Virginia, USA
October 04-October 06
ISBN: 0-7695-2706-X
Abhijit Jas, Intel Corporation
Yi-Shing Chang, Intel Corporation
Sreejit Chakravarty, Intel Corporation
Functional constraints are an integral part of the VLSI design methodology. Pseudofunctional scan ATPG and untestable fault identification are two areas in test where functional constraints are widely used. The number and complexity of these constraints for large designs become a limiting factor in their successful usage. In this paper we define a constraint minimization problem and present a powerful framework to simplify such constraints. The feasibility and effectiveness of this approach is demonstrated by using untestability analysis of large industrial benchmarks as a case study.
Citation:
Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty, "An Approach to Minimizing Functional Constraints," dft, pp.215-226, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006
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