Online Testable Reversible Logic Circuit Design using NAND Blocks

D
DFT
2004
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)
Abstract - Online Testable Reversible Logic Circuit Design using NAND Blocks

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	Similar Articles Articles by D. P. Vasudevan Articles by P. K. Lala Articles by J. P. Parkerson

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)

Cannes, France

October 10-October 13

ISBN: 0-7695-2241-6

	ASCII Text	x
	D. P. Vasudevan, P. K. Lala, J. P. Parkerson, "Online Testable Reversible Logic Circuit Design using NAND Blocks," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 324-331, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004.

	BibTex	x
	@article{ 10.1109/DFT.2004.47, author = {D. P. Vasudevan and P. K. Lala and J. P. Parkerson}, title = {Online Testable Reversible Logic Circuit Design using NAND Blocks}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2004}, issn = {1550-5774}, pages = {324-331}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2004.47}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Online Testable Reversible Logic Circuit Design using NAND Blocks SN - 1550-5774 SP324 EP331 A1 - D. P. Vasudevan, A1 - P. K. Lala, A1 - J. P. Parkerson, PY - 2004 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

D. P. Vasudevan, University of Arkansas, Fayetteville

P. K. Lala, University of Arkansas, Fayetteville

J. P. Parkerson, University of Arkansas, Fayetteville

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.47

A technique for on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide online testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.

Citation:

D. P. Vasudevan, P. K. Lala, J. P. Parkerson, "Online Testable Reversible Logic Circuit Design using NAND Blocks," dft, pp.324-331, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004

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