The paper describes an ABCD modeling approach of a victim interconnect that takes into account the crosstalk coupling effect due to aggressor line in deep sub-micron chips. After the order reduction the crosstalk model is utilized for the analysis of crosstalk coupling effect on the victim's output signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure in prior the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling effect introduces the delay in the victim's output signal which can be significant enough or even unacceptable if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to under-etching or even, length of the victim interconnect is increased because of improper layouts / routing. Influences of other interconnect parasitics on the victim's output signal can also be tested using the same model. Simulation results obtained with our reduced order model is found to be quite good and comparable to the accuracy of the PSPICE simulation.