19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04) Designs for Reducing Test Time of Distributed Small Embedded SRAMs Cannes, France October 10-October 13 ISBN: 0-7695-2241-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.25
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in [An efficient BIST method for small buffers, An efficient BIST method for distributed small buffers]. The improvements are mainly two-fold. On one hand, the testing of time-consuming Data Retention Faults (DRFs), that is neglected by the test architecture in [An efficient BIST method for small buffers, An efficient BIST method for distributed small buffers], is now considered and performed via a DFT technique referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a parallel Local Response Analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained in [An efficient BIST method for small buffers, An efficient BIST method for distributed small buffers], with a negligible area cost.
Index Terms:
Distributed Small Embedded SRAMs, Data Retention Fault Test, Response Analysis, Test Time
Citation:
Baosheng Wang, Yuejian Wu, Andr? Ivanov, "Designs for Reducing Test Time of Distributed Small Embedded SRAMs," dft, pp.120-128, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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