19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04) Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs Cannes, France October 10-October 13 ISBN: 0-7695-2241-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.19
We propose a concurrent error detection (CED) scheme for a sequential circuit implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today?s FPGAs. The proposed scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that results in an incorrect state or output of the circuit. Such faults are detected with no latency. The experimental results show that despite the heterogeneous structure of the proposed CED scheme, the overhead is very reasonable. For the examined benchmark circuits, the combined overhead, that accounts for both extra EMBs and extra logic cells, is in the range of 25.6% to 61.0%, with an average value of 38.6%.
Citation:
Andrzej Krasniewski, "Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs," dft, pp.487-495, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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