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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS
January 23-January 25
ISBN: 978-0-7695-3110-6
ASCII Text
x 
 
Bastien Giraud, Amara Amara, "Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 201-204, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.
 
 
BibTex
x
 
@article{ 10.1109/DELTA.2008.98,
author = {Bastien Giraud and Amara Amara},
title = {Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3110-6},
pages = {201-204},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.98},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS
SN - 978-0-7695-3110-6
SP201
EP204
A1 - Bastien Giraud,
A1 - Amara Amara,
PY - 2008
KW - SRAM cell
KW - Double Gate (DG)
KW - Static Noise Margin (SNM)
KW - Write Margin (WM)
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
This paper presents a comparative study of sub-32 nm CMOS 6T SRAM cells in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar self-aligned gates. Both independent- and connected-gate operation is analysed by modulating the drain current with both front and back gate voltages. The four studied cells take advantage of their transistor back gates to improve stability while optimizing write operation. These are the two key criteria used in the presented sizing method. The results of read-, retention- and write margins and area are displayed for all cells in the presence of process variability.
Index Terms:
SRAM cell, Double Gate (DG), Static Noise Margin (SNM), Write Margin (WM)
Citation:
Bastien Giraud, Amara Amara, "Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS," delta, pp.201-204, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008
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