A Prevenient Voltage Stress Test Method for High Density Memory

D
DELTA
2008
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
Abstract - A Prevenient Voltage Stress Test Method for High Density Memory

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	Jongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang, "A Prevenient Voltage Stress Test Method for High Density Memory," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 516-520, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.93, author = {Jongsoo Yim and Gunbae Kim and Incheol Nam and Sangki Son and Jonghyoung Lim and Hwacheol Lee and Sangseok Kang and Byungheon Kwak and Jinseok Lee and Sungho Kang}, title = {A Prevenient Voltage Stress Test Method for High Density Memory}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {516-520}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.93}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A Prevenient Voltage Stress Test Method for High Density Memory SN - 978-0-7695-3110-6 SP516 EP520 A1 - Jongsoo Yim, A1 - Gunbae Kim, A1 - Incheol Nam, A1 - Sangki Son, A1 - Jonghyoung Lim, A1 - Hwacheol Lee, A1 - Sangseok Kang, A1 - Byungheon Kwak, A1 - Jinseok Lee, A1 - Sungho Kang, PY - 2008 KW - voltage stress test KW - acceleration factor KW - burn-in test KW - junction temperature KW - reliability KW - constant voltage stress KW - voltage ramp stress VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.93

The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).

Index Terms:

voltage stress test, acceleration factor, burn-in test, junction temperature, reliability, constant voltage stress, voltage ramp stress

Citation:

Jongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang, "A Prevenient Voltage Stress Test Method for High Density Memory," delta, pp.516-520, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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