A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	Thomas Lenart, Henrik Svensson, Viktor ?wall, "A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 398-404, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.85, author = {Thomas Lenart and Henrik Svensson and Viktor ?wall}, title = {A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {398-404}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.85}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing SN - 978-0-7695-3110-6 SP398 EP404 A1 - Thomas Lenart, A1 - Henrik Svensson, A1 - Viktor ?wall, PY - 2008 KW - Network-on-Chip KW - 2D Mesh KW - TLM KW - Reconfigurable Computing KW - SCENIC VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Thomas Lenart

Henrik Svensson

Viktor ?wall

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.85

This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (Scenic) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.

Index Terms:

Network-on-Chip, 2D Mesh, TLM, Reconfigurable Computing, SCENIC

Citation:

Thomas Lenart, Henrik Svensson, Viktor ?wall, "A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing," delta, pp.398-404, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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