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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
A Visual Notation for Processor and Resource Scheduling
January 23-January 25
ISBN: 978-0-7695-3110-6
ASCII Text
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Christopher T. Johnston, Paul Lyons, Donald G. Bailey, "A Visual Notation for Processor and Resource Scheduling," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 296-301, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.
 
 
BibTex
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@article{ 10.1109/DELTA.2008.76,
author = {Christopher T. Johnston and Paul Lyons and Donald G. Bailey},
title = {A Visual Notation for Processor and Resource Scheduling},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3110-6},
pages = {296-301},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.76},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - A Visual Notation for Processor and Resource Scheduling
SN - 978-0-7695-3110-6
SP296
EP301
A1 - Christopher T. Johnston,
A1 - Paul Lyons,
A1 - Donald G. Bailey,
PY - 2008
KW - Visual Languages
KW - FPGA
KW - Hardware design Languages
KW - Image Processing
KW - Finite state machines
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
Scheduling of concurrent processors in a real-time image processing system on FPGA (Field programmable gate array) hardware is a not a trivial task. We propose a number of graphical representations for scheduling which were evaluated for use in a visual language for image processing on FPGAs. The proposed representations are illustrated and their strengths and weakness discussed and the reasons for adoption of the state chart notation are given.
Index Terms:
Visual Languages, FPGA, Hardware design Languages, Image Processing, Finite state machines
Citation:
Christopher T. Johnston, Paul Lyons, Donald G. Bailey, "A Visual Notation for Processor and Resource Scheduling," delta, pp.296-301, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008
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