A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

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	Similar Articles Articles by M. Yap San Min Articles by P. Maurine Articles by M. Bastian Articles by M. Robert

4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	M. Yap San Min, P. Maurine, M. Bastian, M. Robert, "A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 107-110, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.72, author = {M. Yap San Min and P. Maurine and M. Bastian and M. Robert}, title = {A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {107-110}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.72}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM SN - 978-0-7695-3110-6 SP107 EP110 A1 - M. Yap San Min, A1 - P. Maurine, A1 - M. Bastian, A1 - M. Robert, PY - 2008 KW - dummy bitline driver KW - low power KW - self-timed memory KW - SRAM KW - statistical design VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.72

Aggressive scaling of transistors is often accompanied by an increase in variability of its intrinsic parameters. In this paper, we point out the importance of considering sensitivity performances due to process variations during SRAM design. We propose a novel dummy bitline driver, an essential component in a self timed memory, which is less sensitive to process variations. A statistical sizing method of this dummy bitline driver is introduced so as to improve the read timing margin, while ensuring a high timing yield. The memory considered is a 256kb SRAM design in 90nm technology node.

Index Terms:

dummy bitline driver, low power, self-timed memory, SRAM, statistical design

Citation:

M. Yap San Min, P. Maurine, M. Bastian, M. Robert, "A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM," delta, pp.107-110, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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