A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	Xiaoxiao Zhang, Amine Bermak, Farid Boussaid, A. Bouzerdoum, "A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 374-377, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.66, author = {Xiaoxiao Zhang and Amine Bermak and Farid Boussaid and A. Bouzerdoum}, title = {A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {374-377}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.66}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks SN - 978-0-7695-3110-6 SP374 EP377 A1 - Xiaoxiao Zhang, A1 - Amine Bermak, A1 - Farid Boussaid, A1 - A. Bouzerdoum, PY - 2008 KW - Face detection KW - Shunting Inhibitory Convolutional Neural Networks KW - VLSI Systolic methodology VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.66

In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. The proposed architectureis based on a VLSI-friendly implementation of Shunting Inhibitory Convolutional Neural Networks (SICoNN). Reported experimental results show that the proposed architecture can detect faces with93% detection accuracy at 5% false alarm rate. A VLSI Systolic architecture was considered to further optimize the design in terms of execution speed, power dissipation and area. Potential applications of the proposed face detection hardware include consumer electronics, security, monitoring and head-counting.

Index Terms:

Face detection, Shunting Inhibitory Convolutional Neural Networks, VLSI Systolic methodology

Citation:

Xiaoxiao Zhang, Amine Bermak, Farid Boussaid, A. Bouzerdoum, "A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks," delta, pp.374-377, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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