The test pattern generator (TPG) in deterministic BIST often suffers from some problems such as extra test power consumption, area overhead and idle test cycles. In this paper, an efficient algorithm is proposed to synthesize a built-in TPG from low power deterministic test patterns without inserting any redundancy test vectors. The structure of TPG is based on the non-uniform cellular automata (CA) and is used to test combinational circuits. And the algorithm is based on the nearest neighborhood model, which can find an optimal non-uniform CA topology to generate given low power test patterns. Simulation results using benchmark combinational circuits show that the generator is efficient to generate the deterministic test patterns in terms of power consumption, area overhead and test time.