Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance

D
DELTA
2008
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
Abstract - Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee, "Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 222-227, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.60, author = {Raimund Ubar and Sergei Devadze and Maksim Jenihhin and Jaan Raik and Gert Jervan and Peeter Ellervee}, title = {Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {222-227}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.60}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance SN - 978-0-7695-3110-6 SP222 EP227 A1 - Raimund Ubar, A1 - Sergei Devadze, A1 - Maksim Jenihhin, A1 - Jaan Raik, A1 - Gert Jervan, A1 - Peeter Ellervee, PY - 2008 KW - fault tolerance KW - fault simulation KW - high-level decision diagrams VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.60

In this paper, a new hierarchical multi-level technique for malicious fault list generation for evaluating the fault tolerance is presented. For the description of the system three levels are exploited: behavioral, functional signal path and structural gate-network levels, whereasat each level the model of decision diagrams and uniform fault analysis procedures are used. Maliciousfaults are found by top-down technique, keeping the complexity of candidate fault sets at each level as low as possible.

Index Terms:

fault tolerance, fault simulation, high-level decision diagrams

Citation:

Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee, "Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance," delta, pp.222-227, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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