4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance
January 23-January 25
ISBN: 978-0-7695-3110-6
In this paper, a new hierarchical multi-level technique for malicious fault list generation for evaluating the fault tolerance is presented. For the description of the system three levels are exploited: behavioral, functional signal path and structural gate-network levels, whereasat each level the model of decision diagrams and uniform fault analysis procedures are used. Maliciousfaults are found by top-down technique, keeping the complexity of candidate fault sets at each level as low as possible.
Index Terms:
fault tolerance, fault simulation, high-level decision diagrams
Citation:
Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee, "Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance," delta, pp.222-227, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008