An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Weiguang Sheng Articles by Liyi Xiao Articles by Zhigang Mao

4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	Weiguang Sheng, Liyi Xiao, Zhigang Mao, "An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 587-591, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.36, author = {Weiguang Sheng and Liyi Xiao and Zhigang Mao}, title = {An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {587-591}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.36}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling SN - 978-0-7695-3110-6 SP587 EP591 A1 - Weiguang Sheng, A1 - Liyi Xiao, A1 - Zhigang Mao, PY - 2008 KW - simulated fault injection KW - soft error KW - stratified sampling KW - reliability KW - VLSI VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Weiguang Sheng

Liyi Xiao

Zhigang Mao

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.36

Soft errors, a concern for space applications in the past, became a critical issue in deep sub-micron VLSI design for the continuous technology scaling. An automated fault injection technique is employed to characterise the recovery coverage and soft error sensitivity of the VHDL based design. Lexical and syntax analysis technique is developed to perform automated fault injection task. Stratified sampling technique is used to reduce the fault injection overheads. A fault injector, HSECT (HIT Soft Error Characterization Toolkit) is developed and 3,000 soft errors are injected into a simple RISC processor, DP32-processor. The recovery coverage and soft error sensitivity of the processor are also further investigated to direct the future design of the fault-tolerant and dependable circuit.

Index Terms:

simulated fault injection, soft error, stratified sampling, reliability, VLSI

Citation:

Weiguang Sheng, Liyi Xiao, Zhigang Mao, "An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling," delta, pp.587-591, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.