A High Speed CMOS Transmitter and Rail-to-Rail Receiver

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu, "A High Speed CMOS Transmitter and Rail-to-Rail Receiver," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 67-70, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.32, author = {Feng Zhang and Zongren Yang and Wei Feng and Hao Cui and Lingyi Huang and Weiwu Hu}, title = {A High Speed CMOS Transmitter and Rail-to-Rail Receiver}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {67-70}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.32}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A High Speed CMOS Transmitter and Rail-to-Rail Receiver SN - 978-0-7695-3110-6 SP67 EP70 A1 - Feng Zhang, A1 - Zongren Yang, A1 - Wei Feng, A1 - Hao Cui, A1 - Lingyi Huang, A1 - Weiwu Hu, PY - 2008 KW - LVDS rail-to-rail VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Hao Cui

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.32

This paper presents a high speed low voltage differential signal (LVDS) interface circuit for CPU, LCD, FPGA and other fast links. In the proposed transmitter a stabile reference and a common mode feedback circuit are applied into the LVDS drivers, which enable the transmitter to tolerate the variations of process, temperature and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture which allows a 1.6G b/s transmission. The transmitter and receiver are implemented in??HJ TC 3.3 v, 0.18 ? CMOS technology. Transmission operations up to 1.6 Gb/s with random data patterns were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 35 mW and 6 mW respectively.

Index Terms:

LVDS rail-to-rail

Citation:

Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu, "A High Speed CMOS Transmitter and Rail-to-Rail Receiver," delta, pp.67-70, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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