Testing NoC-based systems mainly relies on reusing the Network-on-Chip architecture as the test access mechanism (TAM). This, however, implies that the core's test wrapper is supplied with full NoC channel width even if there is a mismatch between the two. How to effectively and efficiently make better utilization of the NoC channels for test data transferring is therefore an interesting and challenging problem. In this paper, we propose to combine a new wrapper design with interleaved test scheduling. Compared to [8], the proposed method can achieve better NoC channel utilization for test without manipulating test frequencies, which not only reduces test power, but also saves design effort for the test engineers. Consequently, the testing time of the NoC-based system is considerably reduced with the proposed technique (especially under stringent power constraints), as shown in the experimental results on circuits crafted from ITC02 benchmarks.