4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008) FPGA implementation of a Single Pass Connected Components Algorithm January 23-January 25 ISBN: 978-0-7695-3110-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.21
The classic connected components labelling algorithm requires two passes through an image. This paper presents an algorithm that allows the connected components to be analysed in a single pass by gathering data on the regions as they are built. This avoids the need for buffering the image, making it ideally suited for processing streamed images on an FPGA or other embedded system with limited memory. An FPGA-based implementation is described, emphasising the modifications made to the algorithm to enable it to satisfy timing constraints.
Index Terms:
Connected Components Analysis, Image Segmentation, Stream Processing, FPGA
Citation:
Christopher T. Johnston, Donald G. Bailey, "FPGA implementation of a Single Pass Connected Components Algorithm," delta, pp.228-231, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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