Design of High-Speed Floating Point Multiplier

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga, "Design of High-Speed Floating Point Multiplier," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 285-289, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.19, author = {Saroja V. Siddamal and R. M. Banakar and B. C. Jinaga}, title = {Design of High-Speed Floating Point Multiplier}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {285-289}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.19}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Design of High-Speed Floating Point Multiplier SN - 978-0-7695-3110-6 SP285 EP289 A1 - Saroja V. Siddamal, A1 - R. M. Banakar, A1 - B. C. Jinaga, PY - 2008 KW - FP operations KW - Fast Carry look ahead adder (MCLA) KW - CSD algorithm KW - Booth algorithm. VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Saroja V. Siddamal

R. M. Banakar

B. C. Jinaga

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.19

Floating-point (FP) multiplication finds application in image and signal processing. This paper presents a hardware implementation of optimized IEEE 754 single precision floating-point multiplier. The design is simulated using Modelsim and synthesized using Virtix E Xilinx ISE. An improvement of 57.77% in area and 44.52% in delay is shown.

Index Terms:

FP operations, Fast Carry look ahead adder (MCLA), CSD algorithm, Booth algorithm.

Citation:

Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga, "Design of High-Speed Floating Point Multiplier," delta, pp.285-289, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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