4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008) Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures January 23-January 25 ISBN: 978-0-7695-3110-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.18
Network-on-chip (NoC) architectures provide a high-performance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput, and hence are suitable for NoC architectures with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication paths, and allocates a proper bandwidth for each communication path. Simulation results show that our design provides an effective solution for a critical step in the NoC design. The cost and latency of the switch in the circuit-switched network can be lowered down with our scheme.
Index Terms:
network-on-chip architectures, circuit-switched networks, mapping, scheduling
Citation:
Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee, "Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures," delta, pp.415-420, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||