A Design of the Frequency Synthesizer for UWB Application in 0.13 ?m RF CMOS Process

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	JinKyung Kim, Sung-Kyu Jung, Ji-Hoon Jung, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam, Bong-Hyuk Park, Sang-sung Choi, "A Design of the Frequency Synthesizer for UWB Application in 0.13 ?m RF CMOS Process," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 441-445, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.128, author = {JinKyung Kim and Sung-Kyu Jung and Ji-Hoon Jung and Sang-Kyung Sung and Kang-Yoon Lee and Chul Nam and Bong-Hyuk Park and Sang-sung Choi}, title = {A Design of the Frequency Synthesizer for UWB Application in 0.13 ?m RF CMOS Process}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {441-445}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.128}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A Design of the Frequency Synthesizer for UWB Application in 0.13 ?m RF CMOS Process SN - 978-0-7695-3110-6 SP441 EP445 A1 - JinKyung Kim, A1 - Sung-Kyu Jung, A1 - Ji-Hoon Jung, A1 - Sang-Kyung Sung, A1 - Kang-Yoon Lee, A1 - Chul Nam, A1 - Bong-Hyuk Park, A1 - Sang-sung Choi, PY - 2008 KW - Frequency Synthesizer KW - phase-locked loop (PLL) KW - single-sideband (SSB) mixer KW - UWB VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.128

This paper describes a 3 to 5GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra-Wideband) application using 0.13 ?m CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper.

Index Terms:

Frequency Synthesizer, phase-locked loop (PLL), single-sideband (SSB) mixer, UWB

Citation:

JinKyung Kim, Sung-Kyu Jung, Ji-Hoon Jung, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam, Bong-Hyuk Park, Sang-sung Choi, "A Design of the Frequency Synthesizer for UWB Application in 0.13 ?m RF CMOS Process," delta, pp.441-445, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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