4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008) Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA January 23-January 25 ISBN: 978-0-7695-3110-6
The paper presents a novel method of evaluating the square root function in FPGA. The method uses a linear approximation subsystem with a reduced size of a look-up table. The reduction in the size of the lookup table is twofold. Firstly, a simple linear approximation subsystem uses the lookup table only for the node points. Secondly, a concept of a variable step look-up table is introduced, where the node points are not uniformly spaced, but the spacing is determined by how close to the linear function the approximated function is. The proposed method of evaluating nonlinear function and specifically the square root function is practical for word lengths of up to 24 bits. The evaluation is performed in one clock cycle.
Index Terms:
FPGA, square root, nonlinear function
Citation:
Stefan Lachowicz, Hans-J? Pfleiderer, "Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA," delta, pp.474-477, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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