Crosstalk is a complex function of signal activity, coupling parasitics, and signal timing. In this work, in the context of high-level synthesis, we propose simulated annealing (SA) based exploration of bus binding, bus-line re-ordering, and data transfer invert encoding schemes that targets the minimization of crosstalk producing signal activity in on-chip buses. Given a data flow graph, we perform execution profiling, operation scheduling, resource allocation, and operation binding. Then, we submit the partially synthesized design to the SA engine which simultaneously explores the binding, re-ordering, and encoding subspace. Experimental results on three benchmarks yielded activity savings in the range of 17-43% with an average of 25% at little (maximum 1%) or no expense of area.