Implementing arithmetic-heavy applications such as filters or neural networks in FPGAs relies to a great extent on the realization of efficient multipliers. However, implementing high-precision multipliers only with configurable logic leads to a large lookup-table usage and considerable routing efforts. Thus, hard-wired multiplier blocks are embedded in modern FPGA devices in order to relieve the resources, but their word-length is still fixed to e.g. 18x18-bit in the Xilinx Virtex-IV DSP48 slices. In this paper, we describe our approach of creating configurable blocks suitable for multi-precision multiplication with a word-length that can be changed at run-time. We present a novel block-serial design that shows a 60% area advantage over a fully parallel multiplier and also a larger structure that can be partitioned into several fully functional smaller multipliers working simultaneously in different configurations.