VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher

D
DELTA
2008
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
Abstract - VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher

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4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

January 23-January 25

ISBN: 978-0-7695-3110-6

	ASCII Text	x
	C. Tanougast, S. Weber, G. Millerioux, J. Daafouz, A. Bouridane, "VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 386-389, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008.

	BibTex	x
	@article{ 10.1109/DELTA.2008.10, author = {C. Tanougast and S. Weber and G. Millerioux and J. Daafouz and A. Bouridane}, title = {VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3110-6}, pages = {386-389}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher SN - 978-0-7695-3110-6 SP386 EP389 A1 - C. Tanougast, A1 - S. Weber, A1 - G. Millerioux, A1 - J. Daafouz, A1 - A. Bouridane, PY - 2008 KW - VLSI design KW - FPGA KW - Cryptography system KW - self-synchronising stream cipher VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2008.10

In this paper, we propose a VLSI architecture and an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream cipher encryption based on a switched linear congruent pseudo-random generator. This encryption, which is based on a chaotic scheme, is particularly attractive since it provides the same security as any conventional self-synchronizing stream cipher requiring only additions, subtractions, multiplications and word-switch operations. We show its feasibility and its implementation which are presented and detailed by using Altera FPGA technology for a set of parameter numbers (switching and key component number). We also show the parametrable of the HME in order to obtain the appropriate security and a the best trade off between the smallest FPGA logical area and the best throughputs rate for embedded applications.

Index Terms:

VLSI design, FPGA, Cryptography system, self-synchronising stream cipher

Citation:

C. Tanougast, S. Weber, G. Millerioux, J. Daafouz, A. Bouridane, "VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher," delta, pp.386-389, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008

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