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Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)
Test Cost Saving and Challenges in the Implementation of x6 and x8 Parallel Testing on Freescale 16-bit HCS12 Micro-controller Product Family
Kuala Lumpur, Malaysia
January 17-January 19
ISBN: 0-7695-2500-8
ASCII Text
x 
 
Lew Boon Kian, "Test Cost Saving and Challenges in the Implementation of x6 and x8 Parallel Testing on Freescale 16-bit HCS12 Micro-controller Product Family," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 74-82, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/DELTA.2006.85,
author = {Lew Boon Kian},
title = {Test Cost Saving and Challenges in the Implementation of x6 and x8 Parallel Testing on Freescale 16-bit HCS12 Micro-controller Product Family},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2006},
isbn = {0-7695-2500-8},
pages = {74-82},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.85},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - Test Cost Saving and Challenges in the Implementation of x6 and x8 Parallel Testing on Freescale 16-bit HCS12 Micro-controller Product Family
SN - 0-7695-2500-8
SP74
EP82
A1 - Lew Boon Kian,
PY - 2006
KW - null
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
Lew Boon Kian, Freescale Semiconductor, Petaling Jaya, Selangor, Malaysia
One of the pressing issues faced by the semiconductor industry today is the cost of testing, especially on the low cost and high volume Microcontroller (MCU) supply to automotive market. This paper describes the general consideration and justification made on the investment of tester, handler and device interface board (DIB) to enable the x6 and x8 multi-site testing on the 80 and 112pin counts 16-bit HCS12 MCU in quad flat pack (QFP) package and the associate test cost reduction and tester saving estimation. Test issue encounter on the first spin of x6 and x8 DIB and how it was resolved through re-design of the DIB also is presented. This finding also provide the PCB designer the valuable information on the constraint of trace length and component layout one need to take into consideration when design a multisite DIB use for high speed MCU testing to avoid AC or DC test failure induced by excessive capacitive loading and resistance drop over signal trace on the DIB.
Citation:
Lew Boon Kian, "Test Cost Saving and Challenges in the Implementation of x6 and x8 Parallel Testing on Freescale 16-bit HCS12 Micro-controller Product Family," delta, pp.74-82, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006
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