Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Peter J. Green Articles by Desmond P. Taylor

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

Kuala Lumpur, Malaysia

January 17-January 19

ISBN: 0-7695-2500-8

	ASCII Text	x
	Peter J. Green, Desmond P. Taylor, "Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 89-92, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006.

	BibTex	x
	@article{ 10.1109/DELTA.2006.56, author = {Peter J. Green and Desmond P. Taylor}, title = {Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2006}, isbn = {0-7695-2500-8}, pages = {89-92}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.56}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array SN - 0-7695-2500-8 SP89 EP92 A1 - Peter J. Green, A1 - Desmond P. Taylor, PY - 2006 KW - null VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Peter J. Green, University of Canterbury, New Zealand

Desmond P. Taylor, University of Canterbury, New Zealand

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.56

This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 Pro Field Programmable Gate Array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO)wireless systems. Each receiver has a Freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed.

Citation:

Peter J. Green, Desmond P. Taylor, "Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array," delta, pp.89-92, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.