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Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)
Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors
Kuala Lumpur, Malaysia
January 17-January 19
ISBN: 0-7695-2500-8
ASCII Text
x 
 
Peter J. Green, Desmond P. Taylor, "Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 466-471, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/DELTA.2006.55,
author = {Peter J. Green and Desmond P. Taylor},
title = {Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2006},
isbn = {0-7695-2500-8},
pages = {466-471},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.55},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors
SN - 0-7695-2500-8
SP466
EP471
A1 - Peter J. Green,
A1 - Desmond P. Taylor,
PY - 2006
KW - null
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
Peter J. Green, University of Canterbury, New Zealand
Desmond P. Taylor, University of Canterbury, New Zealand

This paper describes the concept, architecture, development and demonstration of a high performance, 4 transmitter, real-time space time encoder designed for research into transmitter diversity and multiple input and multiple output (MIMO)wireless systems. It is implemented on a Xilinx Virtex 2 Pro Field Programmable Gate Array (FPGA) and parallel processing on multiple Freescale DSP56321 digital signal processors (DSP). The system is software defined to allow for flexibility in the choice of transmit modulation formats, data rates and space-time coding schemes. Hardware, firmware and software aspects of the space time encoder system to meet design requirements are discussed. The testing and demonstration of the system running the Alamouti space time coding scheme is covered.

The current implementation is an enhancement to an existing Smart Antenna Software RAdio Test System (SASRATS) platform [3, 4] designed to test and verify various space time architectures and algorithms. Of significant interest is the real-time testing of the space time (ST) coding schemes developed by Alamouti [1] and others mentioned in [2]. Space time coding schemes are necessary to support the high data rates of future wireless mobile and local area network standards. The primary objective is to increase system capacity and performance through the use of multiple antennas, spatial multiplexing and space time (ST) coding.

Citation:
Peter J. Green, Desmond P. Taylor, "Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors," delta, pp.466-471, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006
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