Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space

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	Similar Articles Articles by Melanie Po-Leen Ooi

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

Kuala Lumpur, Malaysia

January 17-January 19

ISBN: 0-7695-2500-8

	ASCII Text	x
	Melanie Po-Leen Ooi, "Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 41-46, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006.

	BibTex	x
	@article{ 10.1109/DELTA.2006.52, author = {Melanie Po-Leen Ooi}, title = {Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2006}, isbn = {0-7695-2500-8}, pages = {41-46}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.52}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space SN - 0-7695-2500-8 SP41 EP46 A1 - Melanie Po-Leen Ooi, PY - 2006 KW - null VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Melanie Po-Leen Ooi, Monash University Malaysia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.52

Face detection is the process of locating the position where faces are present in an image. Not all proposed face detection methods are suitable for direct hardware implementation. This paper explains a method that utilises the Reversible Component Transformation (RCT) colour space and outlines its transition from a software- to hardware-based implementation. The hardware performance and efficiency of the RCT algorithm is examined using the Xilinx Virtex-II Field Programmable Gate Arrays (FPGA). Results show that there is almost negligible difference in performance after transition to hardware and its implementation on FPGA requires 255,416 NAND gates, which is only slightly more than twice the number of NAND gates of a basic video-in application.

Citation:

Melanie Po-Leen Ooi, "Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space," delta, pp.41-46, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006

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