A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors

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	Similar Articles Articles by Zhuoyu Bao Articles by Suriya A. Kumar Articles by David M. Wu Articles by Vimal K. Natarajan Articles by Mike Lin

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

Kuala Lumpur, Malaysia

January 17-January 19

ISBN: 0-7695-2500-8

	ASCII Text	x
	Zhuoyu Bao, Suriya A. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin, "A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 57-63, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006.

	BibTex	x
	@article{ 10.1109/DELTA.2006.5, author = {Zhuoyu Bao and Suriya A. Kumar and David M. Wu and Vimal K. Natarajan and Mike Lin}, title = {A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2006}, isbn = {0-7695-2500-8}, pages = {57-63}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.5}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors SN - 0-7695-2500-8 SP57 EP63 A1 - Zhuoyu Bao, A1 - Suriya A. Kumar, A1 - David M. Wu, A1 - Vimal K. Natarajan, A1 - Mike Lin, PY - 2006 KW - null VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Zhuoyu Bao, Intel Corporation

Suriya A. Kumar, Intel Corporation

David M. Wu, Intel Corporation

Vimal K. Natarajan, Intel Corporation

Mike Lin, Intel Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.5

This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by ∼50&. This technique integrates a programmable on-die test generation engine into the Direct Access Test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel high performance microprocessor design.

Citation:

Zhuoyu Bao, Suriya A. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin, "A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors," delta, pp.57-63, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006

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