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Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)
Evaluation time Estimation for Pass Transistor Logic circuits
Kuala Lumpur, Malaysia
January 17-January 19
ISBN: 0-7695-2500-8
ASCII Text
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P.W.C. Prasad, B.I. Mills, A. Assi, S.M.N.A. Senanayake, V.C. Prasad, "Evaluation time Estimation for Pass Transistor Logic circuits," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 422-428, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006.
 
 
BibTex
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@article{ 10.1109/DELTA.2006.47,
author = {P.W.C. Prasad and B.I. Mills and A. Assi and S.M.N.A. Senanayake and V.C. Prasad},
title = {Evaluation time Estimation for Pass Transistor Logic circuits},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2006},
isbn = {0-7695-2500-8},
pages = {422-428},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.47},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - Evaluation time Estimation for Pass Transistor Logic circuits
SN - 0-7695-2500-8
SP422
EP428
A1 - P.W.C. Prasad,
A1 - B.I. Mills,
A1 - A. Assi,
A1 - S.M.N.A. Senanayake,
A1 - V.C. Prasad,
PY - 2006
KW - null
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
P.W.C. Prasad, UAE University, UAE
B.I. Mills, UAE University, UAE
A. Assi, UAE University, UAE
S.M.N.A. Senanayake, Monash University, Malaysia Campus, Malaysia
V.C. Prasad, Multimedia University, Malaysia
This paper describes a mathematical model for the prediction of Binary Decision Diagram (BDD) depth measures, such as the Longest Path Length (LPL) and the Average Path Length (APL). The formal core of the model is a formula for the average LPL and APL over the set of BDD derived from Boolean logic expressions with a given number of variables and product terms. The formula was determined by extensive empirical studies of these measures. The proposed model can provide valuable information about Pass Transistor Logic (PTL) evaluation time for any variable ordering method without building the BDD. Our experimental results show good correlation between the theoretical results and those predicted by the mathematical model, which will greatly reduce the time complexity of applications that use BDDs.
Citation:
P.W.C. Prasad, B.I. Mills, A. Assi, S.M.N.A. Senanayake, V.C. Prasad, "Evaluation time Estimation for Pass Transistor Logic circuits," delta, pp.422-428, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006
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