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Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)
Energy Efficient Cache Tuning with Performance Bound
Kuala Lumpur, Malaysia
January 17-January 19
ISBN: 0-7695-2500-8
Yan Leipo, Nanyang Technological University, Singapore
Siew Kei Lam, Nanyang Technological University, Singapore
Thambipillai Srikanthan, Nanyang Technological University, Singapore
Wu Jigang, Nanyang Technological University, Singapore
Cache memories are the bottle-necks that limit the performance of the processors. In this paper, we present a heuristic algorithm for tuning the level-1 cache. The tuning method searches for the most energy efficient cache configuration under application performance requirement. By simulations we show that the proposed heuristic tuning algorithm is able to find the optimal or near optimal configurations. Algorithm for reducing the number of searched configurations is also proposed.
Citation:
Yan Leipo, Siew Kei Lam, Thambipillai Srikanthan, Wu Jigang, "Energy Efficient Cache Tuning with Performance Bound," delta, pp.97-100, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006
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