Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter

D
DELTA
2004
Second IEEE International Workshop on Electronic Design, Test and Applications
Abstract - Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter

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Second IEEE International Workshop on Electronic Design, Test and Applications

Perth, Australia

January 28-January 30

ISBN: 0-7695-2081-2

	ASCII Text	x
	J. Chandran, R. Kaluri, J. Singh, V. Owall, R. Veljanovski, "Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 77, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004.

	BibTex	x
	@article{ 10.1109/DELTA.2004.10058, author = {J. Chandran and R. Kaluri and J. Singh and V. Owall and R. Veljanovski}, title = {Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2004}, isbn = {0-7695-2081-2}, pages = {77}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10058}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter SN - 0-7695-2081-2 SP EP A1 - J. Chandran, A1 - R. Kaluri, A1 - J. Singh, A1 - V. Owall, A1 - R. Veljanovski, PY - 2004 KW - null VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

J. Chandran, Victoria University

R. Kaluri, Victoria University

J. Singh, Victoria University

V. Owall, Victoria University

R. Veljanovski, Victoria University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10058

A reconfigurable digital root raised cosine (RRC) filter for a UMTS terrestrial radio access (UTRA) mobile terminal receiver is implemented on a Xilinx Vitrex II Pro Field Programmable Gate Array (FPGA). The filter employs a finite impulse response (FIR) and monitors in-band and out-of-band received signal powers and calculates the appropriate filter length that meets the bit-energy to interference ratio (Eb/No) of the system. The results presented are for the time division duplex (TDD) mode of UTRA.

Citation:

J. Chandran, R. Kaluri, J. Singh, V. Owall, R. Veljanovski, "Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter," delta, pp.77, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004

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