Second IEEE International Workshop on Electronic Design, Test and Applications Coverage Measurement for Software Application Level Verification using Symbolic Trajectory Evaluation Techniques Perth, Australia January 28-January 30 ISBN: 0-7695-2081-2
Design verification of a systems-on-a-chip is a bottleneck for hardware design projects. A new solution is a design verification methodology that applies coverage driven verification at the embedded software application level. This methodology currently lacks an appropriate coverage measurement technique. This paper proposes a new coverage model for the software application level. Using this coverage model, a novel technique to represent and measure coverage is described. This technique uses ideas such as control graph structures and checking algorithms to estimate the completeness of software application verification.
Citation:
Adriel Cheng, Atanas Parashkevov, Cheng-Chew Lim, "Coverage Measurement for Software Application Level Verification using Symbolic Trajectory Evaluation Techniques," delta, pp.237, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||