Test Power: a Big Issue in Large SOC Designs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Y. Bonhomme Articles by P. Girard Articles by C. Landrault Articles by S. Pravossoudovitch

The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)

Christchurch, New Zealand

January 29-January 31

ISBN: 0-7695-1453-7

	ASCII Text	x
	Y. Bonhomme, P. Girard, C. Landrault, S. Pravossoudovitch, "Test Power: a Big Issue in Large SOC Designs," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 447, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002.

	BibTex	x
	@article{ 10.1109/DELTA.2002.994670, author = {Y. Bonhomme and P. Girard and C. Landrault and S. Pravossoudovitch}, title = {Test Power: a Big Issue in Large SOC Designs}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2002}, isbn = {0-7695-1453-7}, pages = {447}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994670}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Test Power: a Big Issue in Large SOC Designs SN - 0-7695-1453-7 SP EP A1 - Y. Bonhomme, A1 - P. Girard, A1 - C. Landrault, A1 - S. Pravossoudovitch, PY - 2002 KW - Low Power Testing KW - Test Power KW - BIST KW - Scan KW - DfT VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Y. Bonhomme, Universit? Montpellier II

P. Girard, Universit? Montpellier II

C. Landrault, Universit? Montpellier II

S. Pravossoudovitch, Universit? Montpellier II

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994670

Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this work, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.

Index Terms:

Low Power Testing, Test Power, BIST, Scan, DfT

Citation:

Y. Bonhomme, P. Girard, C. Landrault, S. Pravossoudovitch, "Test Power: a Big Issue in Large SOC Designs," delta, pp.447, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.