The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02) A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications Christchurch, New Zealand January 29-January 31 ISBN: 0-7695-1453-7
Current space applications are pushing for improved on-board processing abilities, in terms of higher computing power, flexibility and fault-resistance, in order to keep up with the huge amount of collected scientific data. Multiprocessor systems seem a viable solution to match these requisites. In particular, systems employing Multistage Interconnection Networks (MINs) offer the advantage of an effective resource allocation, depending on variable workloads and occurrence of faults. The paper presents a fault-tolerant interconnection mechanism, based on redundant MIN, for multi-sensor systems. The proposed system is implemented by means of Field Programmable Gate Arrays (FPGAs) and allows a flexible re-organization of computing resources in dependence of varying operating conditions. Fault-tolerance is achieved both by exploiting the MIN intrinsic redundancy and by using an efficient FPGA re-configuration technique.
Index Terms:
Multistage Interconnection Network, Field programmable Gate Arrays, Fault Tolerance, Space Applications
Citation:
Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi, "A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications," delta, pp.302, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||