Multi-Level Fault Simulation of Digital Systems on Decision Diagrams

D
DELTA
2002
The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Abstract - Multi-Level Fault Simulation of Digital Systems on Decision Diagrams

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Raimund Ubar Articles by Jaan Raik Articles by Eero Ivask Articles by Marina Brik

The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)

Christchurch, New Zealand

January 29-January 31

ISBN: 0-7695-1453-7

	ASCII Text	x
	Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik, "Multi-Level Fault Simulation of Digital Systems on Decision Diagrams," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 86, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002.

	BibTex	x
	@article{ 10.1109/DELTA.2002.994594, author = {Raimund Ubar and Jaan Raik and Eero Ivask and Marina Brik}, title = {Multi-Level Fault Simulation of Digital Systems on Decision Diagrams}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2002}, isbn = {0-7695-1453-7}, pages = {86}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994594}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Multi-Level Fault Simulation of Digital Systems on Decision Diagrams SN - 0-7695-1453-7 SP EP A1 - Raimund Ubar, A1 - Jaan Raik, A1 - Eero Ivask, A1 - Marina Brik, PY - 2002 KW - Digital systems KW - register transfer and gate level descriptions KW - fault simulation KW - decision diagrams VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Raimund Ubar, Tallinn Technical University

Jaan Raik, Tallinn Technical University

Eero Ivask, Tallinn Technical University

Marina Brik, Tallinn Technical University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994594

A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. DDs are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows to reduce time expenses Compared to the traditional gate-level fault simulation approach

Index Terms:

Digital systems, register transfer and gate level descriptions, fault simulation, decision diagrams

Citation:

Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik, "Multi-Level Fault Simulation of Digital Systems on Decision Diagrams," delta, pp.86, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.