This paper describes a test approach for Intellectual Property (IP) analog or mixed-signal cores, which may be used in core-based System-on-Chip (SOC) designs. The proposed method comprises a two-phase test design process. Given an analog/mixed-signal IP core, an equivalent fault analysis is carried out in the initial phase. The main aim is to extract useful insights for improving the BIST and DfT designs which to be conducted in the second phase. An early built-in self-test (BIST) method [9] was able to achieve high fault coverage comparable to the traditional scan techniques. In the second phase, we propose to apply an improved version of this method based on the weighted sum of selected node voltages. Besides high fault coverage, the proposed BIST technique only needs an extra testing output pin and only a single DC stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for the testing environment of IP cores.