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Design, Automation and Test in Europe (DATE'05) Volume 2
Challenges in Embedded Memory Design and Test
Munich, Germany
March 07-March 11
ISBN: 0-7695-2288-2
Erik Jan Marinissen, Philips Research Labs, The Netherlands
Betty Prince, Memory Strategies International, Leander, TX, USA
Doris Keitel-Schulz, Infineon Technologies, Munich, Germany
Yervant Zorian, Virage Logic, Fremont, CA, USA
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to update their knowledge on memories. This Hot Topic paper provides an embedded tutorial on embedded memories, in terms of what is new and coming versus what is old and vanishing, and what are the associated design, test, and repair challenges related to using embedded memories.
Citation:
Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian, "Challenges in Embedded Memory Design and Test," date, vol. 2, pp.722-727, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005
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