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Design, Automation and Test in Europe (DATE'05) Volume 1
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Munich, Germany
March 07-March 11
ISBN: 0-7695-2288-2
Balkaran Gill, Case Western Reserve University, Cleveland, Ohio
Michael Nicolaidis, iRoC Technologies, Grenoble, France
Francis Wolff, Case Western Reserve University, Cleveland, Ohio
Chris Papachristou, Case Western Reserve University, Cleveland, Ohio
Steven Garverick, Case Western Reserve University, Cleveland, Ohio
In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process technology. The BICS reliability analysis for process, voltage, temperature, and power supply noise are provided. This BICS detect various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. This BICS found to be very reliable for process, voltage and temperature variation and under stringent noise conditions.
Citation:
Balkaran Gill, Michael Nicolaidis, Francis Wolff, Chris Papachristou, Steven Garverick, "An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories," date, vol. 1, pp.592-597, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005
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