A Synthesizable IP Core for DVB-S2 LDPC Code Decoding

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Frank Kienle Articles by Torben Brack Articles by Norbert Wehn

Design, Automation and Test in Europe (DATE'05) Volume 3

Munich, Germany

March 07-March 11

ISBN: 0-7695-2288-2

	ASCII Text	x
	Frank Kienle, Torben Brack, Norbert Wehn, "A Synthesizable IP Core for DVB-S2 LDPC Code Decoding," Design, Automation and Test in Europe Conference and Exhibition, vol. 3, pp. 100-105, Design, Automation and Test in Europe (DATE'05) Volume 3, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.39, author = {Frank Kienle and Torben Brack and Norbert Wehn}, title = {A Synthesizable IP Core for DVB-S2 LDPC Code Decoding}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {3}, year = {2005}, issn = {1530-1591}, pages = {100-105}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A Synthesizable IP Core for DVB-S2 LDPC Code Decoding SN - 1530-1591 SP100 EP105 A1 - Frank Kienle, A1 - Torben Brack, A1 - Norbert Wehn, PY - 2005 KW - null VL - 3 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Frank Kienle, University of Kaiserslautern, Germany

Torben Brack, University of Kaiserslautern, Germany

Norbert Wehn, University of Kaiserslautern, Germany

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.39

The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits.

The decoding of LDPC is an iterative process. For DVB-S2 about 300000 messages are processed and reordered in each of the 30 iterations. These huge data processing and storage requirements are a real challenge for the decoder hardware realization, which has to fulfill the specified throughput of 255MBit/s for base station applications.

In this paper we will show, to the best of our knowledge, the first published IP LDPC decoder core for the DVB-S2 standard. We present a synthesizable IP block based on ST Microelectronics 0:13?m CMOS technology.

Citation:

Frank Kienle, Torben Brack, Norbert Wehn, "A Synthesizable IP Core for DVB-S2 LDPC Code Decoding," date, vol. 3, pp.100-105, Design, Automation and Test in Europe (DATE'05) Volume 3, 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.