Design, Automation and Test in Europe (DATE'05) Volume 1 Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures Munich, Germany March 07-March 11 ISBN: 0-7695-2288-2
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.269
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.
Citation:
Suresh Srinivasan, Lin Li, N. Vijaykrishnan, "Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures," date, vol. 1, pp.218-223, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||