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Design, Automation and Test in Europe (DATE'05) Volume 2
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design
Munich, Germany
March 07-March 11
ISBN: 0-7695-2288-2
ASCII Text
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Bharat Sukhwani, Uday Padmanabhan, Janet M. Wang, "Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 758-763, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005.
 
 
BibTex
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@article{ 10.1109/DATE.2005.221,
author = {Bharat Sukhwani and Uday Padmanabhan and Janet M. Wang},
title = {Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {2},
year = {2005},
issn = {1530-1591},
pages = {758-763},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.221},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design
SN - 1530-1591
SP758
EP763
A1 - Bharat Sukhwani,
A1 - Uday Padmanabhan,
A1 - Janet M. Wang,
PY - 2005
KW - null
VL - 2
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Bharat Sukhwani, University of Arizona, Tucson
Uday Padmanabhan, University of Arizona, Tucson
Janet M. Wang, University of Arizona, Tucson
New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's scaling limitations. However, many such devices exhibit non-monotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.
Citation:
Bharat Sukhwani, Uday Padmanabhan, Janet M. Wang, "Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design," date, vol. 2, pp.758-763, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005
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