Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

D
DATE
2005
Design, Automation and Test in Europe (DATE'05) Volume 1
Abstract - Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

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Design, Automation and Test in Europe (DATE'05) Volume 1

Munich, Germany

March 07-March 11

ISBN: 0-7695-2288-2

	ASCII Text	x
	D. C. Keezer, C. Gray, A. Majid, N. Taher, "Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 152-157, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.203, author = {D. C. Keezer and C. Gray and A. Majid and N. Taher}, title = {Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2005}, issn = {1530-1591}, pages = {152-157}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.203}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL SN - 1530-1591 SP152 EP157 A1 - D. C. Keezer, A1 - C. Gray, A1 - A. Majid, A1 - N. Taher, PY - 2005 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

D. C. Keezer, Georgia Institute of Technology, Atlanta, GA

C. Gray, Georgia Institute of Technology, Atlanta, GA

A. Majid, Georgia Institute of Technology, Atlanta, GA

N. Taher, Georgia Institute of Technology, Atlanta, GA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.203

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about ±25ps timing accuracy.

Citation:

D. C. Keezer, C. Gray, A. Majid, N. Taher, "Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL," date, vol. 1, pp.152-157, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005

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