Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

D
DATE
2005
Design, Automation and Test in Europe (DATE'05) Volume 1
Abstract - Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

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Design, Automation and Test in Europe (DATE'05) Volume 1

Munich, Germany

March 07-March 11

ISBN: 0-7695-2288-2

	ASCII Text	x
	Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press, "Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 56-61, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.199, author = {Matthias Beck and Olivier Barondeau and Martin Kaibel and Frank Poehl and Xijiang Lin and Ron Press}, title = {Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2005}, issn = {1530-1591}, pages = {56-61}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.199}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality SN - 1530-1591 SP56 EP61 A1 - Matthias Beck, A1 - Olivier Barondeau, A1 - Martin Kaibel, A1 - Frank Poehl, A1 - Xijiang Lin, A1 - Ron Press, PY - 2005 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Matthias Beck, Infineon Technologies AG, Germany

Olivier Barondeau, Infineon Technologies AG, Germany

Martin Kaibel, Infineon Technologies AG, Germany

Frank Poehl, Infineon Technologies AG, Germany

Xijiang Lin, Mentor Graphics Corporation, Wilsonville, OR

Ron Press, Mentor Graphics Corporation, Wilsonville, OR

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.199

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

Citation:

Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press, "Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality," date, vol. 1, pp.56-61, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005

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