Leakage-Aware Interconnect for On-Chip Network

D
DATE
2005
Design, Automation and Test in Europe (DATE'05) Volume 1
Abstract - Leakage-Aware Interconnect for On-Chip Network

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Design, Automation and Test in Europe (DATE'05) Volume 1

Leakage-Aware Interconnect for On-Chip Network (PDF)

Munich, Germany

March 07-March 11

ISBN: 0-7695-2288-2

	ASCII Text	x
	Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin, "Leakage-Aware Interconnect for On-Chip Network," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 230-231, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.195, author = {Yuh-Fang Tsai and Vijaykrishnan Narayaynan and Yuan Xie and Mary Jane Irwin}, title = {Leakage-Aware Interconnect for On-Chip Network}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2005}, issn = {1530-1591}, pages = {230-231}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.195}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Leakage-Aware Interconnect for On-Chip Network SN - 1530-1591 SP230 EP231 A1 - Yuh-Fang Tsai, A1 - Vijaykrishnan Narayaynan, A1 - Yuan Xie, A1 - Mary Jane Irwin, PY - 2005 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Yuh-Fang Tsai, Penn State University

Vijaykrishnan Narayaynan, Penn State University

Yuan Xie, Penn State University

Mary Jane Irwin, Penn State University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.195

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

Citation:

Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin, "Leakage-Aware Interconnect for On-Chip Network," date, vol. 1, pp.230-231, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005

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