Design, Automation and Test in Europe (DATE'05) Volume 2 Implicit and Exact Path Delay Fault Grading in Sequential Circuits Munich, Germany March 07-March 11 ISBN: 0-7695-2288-2
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.179
The first path implicit and exact non-robust path delay fault grading technique for non-scan sequential circuits is presented. Non enumerative exact coverage is obtained, by allowing any latched error representing a delayed transition to propagate to a primary output with the support of other potentially latched errors. The generalized error propagation is done by symbolic simulation. Appropriate data structures for function manipulation are used. The advantage of the proposed method is demonstrated experimentally with consistent improvement in coverage over an existing pessimistic heuristic despite enforced bounds on the memory requirements.
Citation:
M. M. Vaseekar Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi, "Implicit and Exact Path Delay Fault Grading in Sequential Circuits," date, vol. 2, pp.990-995, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||